Programmable logic devices (“PLDs”) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (“FPGA”), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (“IOBs”), configurable logic blocks (“CLBs”), dedicated random access memory blocks (“BRAMs”), multipliers, digital signal processing blocks (“DSPs”), processors, clock managers, delay lock loops (“DLLs”), and so forth. As used herein, “include” and “including” mean including without limitation.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In CPLDs, configuration data is typically stored on-chip in non-volatile memory. In some CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration (programming) sequence.
For all of these programmable logic devices (PLDs), the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, e.g., using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable. For example, one type of PLD includes a combination of hard-coded transistor logic and a programmable switch fabric that programmably interconnects the hard-coded transistor logic.
Some FPGAs, such as the Virtex FGPA, can be programmed to incorporate blocks with pre-designed functionalities, i.e., “cores”. A core can include a predetermined set of configuration bits that program the FPGA to perform one or more functions. Alternatively, a core can include source code or schematics that describe the logic and connectivity of a design. Typical cores can provide, but are not limited to, digital signal processing (DSP) functions, memories, storage elements, and math functions. Some cores include an optimally floorplanned layout targeted to a specific family of FPGAs. Cores can also be parameterizable, i.e., allowing the user to enter parameters to activate or change certain core functionality.
Turbo channel codes (Turbo codes) conventionally are processed using an interleaver circuit to shuffle input data before encoding by a constituent convolutional encoder. Of note, by Turbo Code coding it is meant convolutional coding in contrast to Product Code coding or Product Codes. To form an interleaved data sequence during such encoding, data is conventionally read from an input buffer in a permutated order according to an interleaved address sequence.
There is a movement to replace prime-permutation interleavers used in 3rd Generation Partnership Project (3GPP) communication systems with Quadratic Permutation Polynomial (QPP) interleavers. QPP interleavers generally are “maximally contention-free” as any factor of the interleaver length may be used as a parallel processing order. Thus, maximally contention-free addressing may facilitate parallel processing during Turbo Code decoding.
QPP interleavers may be used for 3GGP Long Term Evolution (LTE) Turbo Code coding. A QPP interleaver output may be read responsive to an address of interleaved address sequence given by:Π(x)=(f1x+f2x2)mod K  (1)where 0≦x, f1, f2<K. The x-th interleaved output is read from the address given by Equation 1, where K is an information block length and where f1, and f2 are respective coefficients. QPP interleavers may be used for Turbo Codes with either tail-biting or terminated trellising.
Specification of a QPP interleaver may thus be formulated as a quadratic equation using modulo-K arithmetic. This formulation as a quadratic equation facilitates random access to an address sequence directed by computation of the quadratic formula. However, this computation involves multiplication and modulo operations which may be cumbersome. In particular, multiplication and modulo operations may result in relatively large, high-latency circuits when implemented in an FPGA.